Multi-layered solid electrolytic capacitors according to the present invention are used as, for example, chip capacitors mounted on a printed circuit board. Among such multi-layered solid electrolytic capacitors, one employing as its solid electrolyte a TCNQ complex salt or a conductive polymer such as polypyrrole, polythiophene, polyfuran, and polyaniline has drawn attention. As the size reduction of electronic devices advances, demands for the solid electrolytic capacitor with a smaller size and a higher capacity have been escalating. In addition, the recent trend toward faster signal processing speed and lower power consumption in CPUs and the like requires higher frequency and larger current, and these requirements in turn create a strong demand for capacitors with lower ESR.
A conventional multi-layered solid electrolytic capacitor has been fabricated in the following manner. As illustrated in FIG. 15, a dielectric oxide film 42, a solid electrolyte layer 43, a carbon layer 44, and a silver paint layer 45 are successively formed over a portion of the surface of a valve metal 41 (e.g., aluminum) to prepare a capacitor element 46.
Next, as illustrated in FIG. 16, a plurality of the capacitor elements 46 in a stacked state are disposed on one surface of an anode mounting part 51 integrally formed with an anode terminal 52 and on one surface of a cathode mounting part 47 integrally formed with a cathode terminal 48, and thereafter covered with an exterior resin 54. Alternatively, as illustrated in FIG. 17, a plurality of the capacitor elements 46 in a stacked state are disposed on both surfaces of the anode mounting part 51 and on both surfaces of the cathode mounting part 47 and thereafter covered with an exterior resin 54. Through these processes, the multi-layered solid electrolytic capacitor has been fabricated.
When stacking the capacitor element 46, first, a capacitor element 46 is held at its cathode portion 46b (main body part) and conveyed and placed onto a lead frame. Thereafter, the anode portion 46a of the capacitor element 46 is connected to the anode terminal 52 by resistance welding, and then, the connected anode portion 46a of the capacitor element 46 is welded to the anode portion 46a of another capacitor element 46 to be stacked thereover. Meanwhile, the cathodes of the capacitor elements 46 are connected by conductive adhesive 57. The capacitor elements are stacked by repeating the above-described processes (see Patent Reference 1). The purpose of stacking the capacitor elements 46 is to improve the capacitor's capacitance characteristics and reduce its ESR.
[Patent Document 1] Japanese Published Unexamined Patent Application No. 11-135367